1. Field of the Invention
This invention relates to a semiconductor memory device (such as a DRAM and SRAM) having a multibit parallel test function which includes multibit parallel writing and multibit parallel checking functions, and also to a method of testing the multibit parallel test function of such a semiconductor memory.
2. Description of the Prior Art
Recently, semiconductor memory devices tend to have greater storage capacity, and accordingly the test of such devices requires much more time. Hitherto, however, the length of time involved in testing such a memory device has not been of consideration, and, therefore, no importance has been placed on the provision of a circuit for testing multiple bits in parallel. Indeed, no such circuit has been in use. Hence, no method has been developed for testing a multibit parallel testing function incorporated in a semiconductor memory device.
It can be anticipated that with further increases in the storage capacity of a semiconductor memory device, it will be required to reduce the time involved in testing. In such a situation, it may be necessary to incorporate a function of performing a multibit parallel test into one chip together with a semiconductor memory device. In such a semiconductor memory device, it will be necessary to test the multibit parallel test function incorporated in the memory device.